During and after the fabrication of integrated circuits in semiconductor chips such as, e.g., DRAM memory chips, these are generally subject to a functional test. This is intended to ensure that only defect-free and functional devices are supplied. In this case, a distinction is made between two types of tests, product data measurements and parameter data measurements.
Product data measurements are carried out on the finished end product. In this case, a number of different input signals are applied to the circuit integrated in the chip, which result in specific output signals. The combination of input signals are selected such that the tests do not take an excessively long time, but as many functional errors as possible are covered. Thus, in the course of product data measurement, the chip is checked in its entirety with regard to its correct functioning.
By contrast, parameter data measurements are intended to reflect as well as possible the electrical properties of the circuit components integrated in the semiconductor chip. These measurements take place during the process of fabricating the semiconductor chip. In the course of fabricating semiconductor chips, the latter are arranged on a semiconductor wafer. The kerf separates the individual chips from one another.
Test structures are provided in the kerf for the parameter data measurement. The test structures are intended to simulate the behavior of the devices that are integrated in the chip. The test structures of the kerf are externally accessible via contacts. In the course of parameter measurement, important characteristic quantities that are intended to provide information about correct or defective functioning of the devices in the chip are measured at the test structures. Typical characteristic quantities are, e.g., in the case of a memory chip, the threshold voltages of the selection transistors or the magnitude of the capacitance of the memory cell. If a drift of characteristic quantities is ascertained during the fabrication process it is possible to intervene in the production process, and to perform an adjustment of the devices by modifying relevant process variables.
In the further production steps, the semiconductor chips on the wafer are separated by being sawn apart along the kerf, i.e., dicing. In this case, the kerf is lost, and with it the test structures situated therein. This has the disadvantage that, in the event of the defect analysis of semiconductor chips that is generally carried out in the event of customer returns, it is often not possible to ascertain the exact cause of error. Thus, e.g., aging effects that result in the failure of the chips cannot be detected since the test structures at which the parameter data were measured during the production process are no longer available for a renewed measurement. A before/afterward comparison is not possible.
Furthermore, the problem arises that the actual behavior of the devices in the chip can never be determined by measuring parameter data in the kerf. Thus, it is not possible to detect effects due to mutual influencing on account of the small spatial distances between the circuit components in the chip (proximity), crosstalk, etc. Previous tests and defect analysis methods lead to delays in product introduction and difficult qualifications.
An integrated circuit and a method for testing integrated circuits of a semiconductor chip, which allow the functional checking and defect analysis to be configured effectively by nondestructively measuring characteristic electrical parameters of circuit components that are integrated in the semiconductor chip, is desirable.